1. Field of the Invention
This present invention relates to a non-volatile semiconductor memory, more particularly, to a non-volatile semiconductor memory and a method for controlling a non-volatile semiconductor memory using Silicon On Insulator (SOI) technology.
2. Description of the Related Art
A NAND type flash electrically erasable programmable read-only memory (EEPROM) is known as a type of non-volatile semiconductor memory. The NAND type flash EEPROM experiences fluctuations in gate threshold voltage, due to the influence of parasitic capacitance, in the element isolation region between memory cell transistors and parasitic capacitance between an interconnect and a substrate, and the like.
In order to reduce the fluctuation in the gate threshold voltage due to the influence of the parasitic capacitance in the element isolation region and the parasitic capacitance between the interconnect and the substrate, a NAND flash EEPROM has been investigated which employs SOI technology. In this technology, a semiconductor layer (SOI layer) is arranged on a buried insulating layer (buried oxide (BOX) layer), and serves as an active layer.
According to the NAND flash EEPROM employing the SOI technology, the memory cell transistors adjacent to one another in the row direction are isolated from one another by an element isolation insulating film which is buried as deep as the buried insulating layer. This structure reduces the parasitic capacitance in the element isolation region.
In addition, since the SOI layer is formed on the buried insulating layer, the parasitic capacitance between the interconnect and the substrate can be reduced, and hence, the fluctuation in the gate threshold voltage can be reduced.
As memory cell transistors have been miniaturized, an interval between the source region and the drain region of such a memory cell transistor has become so narrower that influence of the short channel effect has increased in the NAND flash EEPROM employing the SOI technology.